Benchmarking

EDA Costs / Designer Benchmark benefits:

  • Unique Benchmark of your EDA software overheads / designer versus the average of your choice of peer group of 4 or more companies
  • Improve market understanding of often the most expensive IC design overhead
  • Includes EDA costs for 4 design sub-categories: Analog Design, Analog Layout, Digital Design & P&R Layout (see sample bar chart below)

  • An on-site discussion of the report is included to provide a second external interpretation of Benchmark findings
  • Scope now broadened to include benchmark of:
    • HPC compute farm budget & infrastructure, in-cloud & on-premise
    • Semiconductor IP costs
    • Design Enablement activities & resources
    • Emulation and FPGA-Prototyping costs
    • Infrastructure for Software Development

NXP Semiconductors : “….This was consultancy as it should be: hands-on advice …. and professional benchmarking.”

Cypress Semiconductor : “I’ve found Gerry to be professional, expert in the field and to deliver quality results. Latest engagements have helped us confirm and modify our current direction. I would participate again given the opportunity.”

edalics’ main emphasis in the benchmarking process is on the two most critical potential pitfalls, the compatibility of the participating companies and the accuracy of the submitted input data.

To request further information simply email: Benchmark@edalics.com